/log

── development journal ──────────────────────────────

• [2026-04-04]RISC-V Core: Finalizing the UVM Testbench — Finished the Scoreboard, Monitor, and Reference Model, as well as added coverage.
• [2026-03-29]RISC-V Core: Refactoring UVM Sequence Architecture — Overhauled the sequence item class hierarchy and added encode functions
• [2026-03-06]RISC-V Core: Building the UVM Testbench — Got a working UVM testbench skeleton running: sequence items, sequences, agent, driver
• [2026-02-26]RISC-V Core: Bug Hunting and Branch Instructions — First real bugs caught by the testbench, all branch/jump/upper immediate instructions added, and UVM begins.
• [2026-02-21]RISC-V Core: R-Type, I-Type, and S-Type Instructions — Heavy implementation week, got the datapath working for R, I, and S-type instructions
• [2026-02-12]RISC-V Core: Upgrading to SystemVerilog — Migrated the whole design from Verilog to SystemVerilog and wrote out the architecture document.
• [2026-01-22]RISC-V Core: Building the Foundation — Started the RISC-V project: ALU, register file, program counter, and instruction memory up and running.